1. Field of the Invention
The present invention relates to multiplexers for controlling a data output sequence and parallel-to-serial converters using the same. More particularly, the present invention disclosed herein relates to technology for easily controlling a bit sequence of serial data output from a parallel-to-serial converter where a plurality of multiplexers are coupled each other in a tree structure, by simply controlling the output sequence of data output from the multiplexers without altering an interconnection structure thereof.
The present invention has been produced from the work supported by the IT R&D program of MIC (Ministry of Information and Communication)/IITA (Institute for Information Technology Advancement) [2005-S075-02, Development of SoC for Wired and Wireless Unified Network] in Korea.
2. Discussion of Related Art
A multiplexer is a kind of electronic circuit component that functions to select one input data signal from a plurality of input data signals and output the selected data signal. A data signal to be selected is determined by an input state of a selection signal. A multiplexer is generally abbreviated to MUX.
FIGS. 1A and 1B are circuit diagrams of conventional multiplexers.
Referring to FIG. 1A, a first input data bit D0 of a multiplexer 100 is latched in latches 110A, 110B, and 110C while a second input data bit D1 is latched in latches 120A and 120B.
The reason for latching the first and second input data bits in the latches 110A, 110B, 110C, 120A, and 120B is: (1) not to generate a glitch at an output Q, even when the two input data bits D0 and D1 vary at the same time; and (2) not to generate a glitch at the output Q, even when the two input data bits D0 and D1 vary at a certain time regardless of a clock signal CLK that is used as a control signal.
In the meantime, it is also possible to employ a multiplexer omitted one of the latches coupled to the input data bit D0 and another of the latches coupled to the input data bit D1, as shown in FIG. 1B, in order to reduce power consumption through the 2:1 multiplexer shown in FIG. 1A.
The 2:1 multiplexer configured as shown in FIGS. 1A and 1B can be employed in a parallel-to-serial converter for transforming parallel data into serial data. A conventional parallel-to-serial converter includes the 2:1 multiplexers coupled in a tree structure for fast operation.
However, as the 2:1 multiplexer is designed such that the first input data bit D0 passes through one more latch than the second input data bit D1 does (refer to FIGS. 1A and 1B), the second input data bit D1 is always output earlier than the first input data bit D0.
In other words, a parallel-to-serial converter with the conventional 2:1 multiplexers formed in a tree structure has a complicated circuit structure, in which it is inevitable that signal lines of parallel data intersect each other to change an output bit sequence, because the bit sequence is fixed when the parallel data is converted into serial data. Furthermore, the complicated circuit structure may create crosstalk between the intersecting signal lines, and increase a semiconductor chip area due to additional interconnections.